I. Field of the Invention
The invention relates in general to a computer-implemented method for electronic design automation (EDA) to generate a layout for a circuit and, in particular, to generate a layout for an analog circuit based on schematics.
II. Description of the Prior Art
Since invented in 1960s, the size of an integrated circuit (IC) has grown quickly. Twenty years ago, an IC might comprise hundreds to thousands of basic cells. Today, an IC may comprise thousands to millions of basic cells.
There are many forms to represent a circuit design; the forms mainly include a netlist and a schematic. A netlist which is described in text form lists all the components and the connections among the components. However, compared with a netlist, a schematic can further include the topology of all the components in the circuit. One could easily understand the structure of a circuit network with the schematic of the circuit network. That is, schematic design flow is a more intuitive way to design the circuit network. As a result, schematic design flow is nowadays broadly taken as a useful method for designing an analog IC.
As the IC nowadays includes thousands to millions of basic cells, it's getting more difficult for an engineer to draw the layout of each of basic cells. Consequently, it is desired to develop methods and/or tools to help engineers in order to reduce the time of drawing a layout. There are some electronic design automation (EDA) tools which are developed to cut short the time of drawing a layout. As described in U.S. Pat. No. 6,574,779, a sub-circuit in a netlist is compared with standard cells in a library. If the circuit structure of the sub-circuit, that is, the basic cells with parameters and the connection relationship thereof, is identical to one of the standard cells, the sub-circuit is recognized as the same as the standard cell; and the layout of the standard cell is then copied and associated to the sub-circuit. With this method, the time of drawing a layout is shortened.
While generating a layout of a digital circuit, a netlist design flow is usually useful because there are typically well-developed standard libraries for translating each gate of the digital circuit to a corresponding standard cell. The reason is that there are few variants of each type of basic functional block and most of them are well described. For example, there are only four types of broadly used full-adders, namely ripple adder, carry-look-ahead adder, carry-select adder, and Manchester chain. Further, in most of the IC design, the ripple adder meets the requirement and that kind of adder is supported and described in the standard library. Hence, netlist design flow is capable for generating the layout of a digital circuit.
However, the netlist design flow is not that powerful for saving the time of drawing a layout of an analog circuit and/or a high performance digital circuit. In an analog circuit design and/or a high performance digital circuit design, the circuit structures are usually different from typical circuit structures described in the standard library. As a result, most circuits in the analog circuit design and/or in the digital circuit design cannot be recognized with the netlist design flow. Thus, time of drawing a layout of an analog circuit and/or a high performance digital circuit can not be significantly reduced by using the netlist design flow.
Therefore, what is needed is a method which can recognize circuits which have similar circuit structures to allow circuit designers to reuse the layouts of those circuit structures. With such method, the time of drawing layout of analog circuits and/or high performance digital circuits can be significantly reduced.